The present invention relates generally to cache controlling devices and methods for controlling caches. That is, the invention relates to devices and methods which control the data traffic between a main storage (medium), a cache storage (medium) and a processor (e.g. a Central Processing Unit (CPU).
Today, cache structures are used in many microprocessors for increasing the performance of the system in which the microprocessor is used.
These cache structures allow for storing frequently used data or program code in a faster accessible cache storage of mostly smaller capacity (e.g. an SRAM memory), such that this data may subsequently be read from the cache storage instead of reading the data for each data access from a slower accessible main storage of mostly larger capacity (e.g. a flash memory or hard-disk). For the sake of simplicity, in the following description, program code may be referred to as data as well.
There may be several reasons for the slower accessibility of the main storage, such as, e.g. a relatively long data path between the main storage and the processor, which typically causes a propagation delay of several clock cycles, or such as a technology-induced relatively long access time of the main storage.
This slower accessibility of the main storage would constitute a bottleneck for the performance of the system comprising the processor and the main storage. Hence, following the principle of locality, an increase in the system performance may be established by coupling a physically faster accessible cache storage in the local proximity of the processor. This yields a shorter data path between the cache storage and the processor. Typically, the cache storage is integrated in the processor and is smaller because of its higher costs per bit storage capacity due to the faster and hence more expensive technology of the cache storage.
Thus, frequently used data may be stored in the cache storage after this data has been accessed by the processor for the first time. As long as this data is stored in the cache storage, for each access operation to this data, the processor does not need to fetch this data from the slowly accessible main storage, but may fetch it from the quickly accessible cache storage.
However, there may be other data, in particular, less frequently used data, which should or must not activate the device controlling the cache storage, that is the cache controller, and which should or must not be stored in the cache storage.
The above-mentioned cache storage principle in general is widely known and a description of fundamentals of cache principles may be found in “Computer Organization and Design”, 3rd Edition, by David A. Patterson and John L. Hennessy published by Morgan Kaufmann.
With respect to the function of the cache controller, this controlling device may use different types of cache controlling mechanisms depending on the application and the architecture of the system comprising the processor, the cache storage and the main storage. These cache controlling mechanisms mainly differ in the method by which the data is sorted or stored into the cache storage.
A common cache controlling mechanism uses the memory address where specific data is stored in the main memory to decide whether or not this specific data should be stored in the cache storage. In other words, this mechanism comprises an analysis of the memory addresses from which the specific data is read. An example of a processor which uses the above-described memory address based cache controlling mechanism is Infineon's TriCore® microcontroller.
However, these memory address based cache controlling mechanisms typically need more memory address space which would actually be necessary for the corresponding amount of data. The reason for this is that some or even all of the data mostly appear at two memory addresses, one memory address being part of a cached memory area and the other memory address being part of uncached memory area. When using a processor the address space of which is limited for architectural reasons, e.g. a C166® microcontroller, the multiple appearance of data in the address space represents an expensive way of cache controlling.
Furthermore, when using a memory address based cache controlling mechanism, an efficient data structure within the cache storage only results if the word width of the cache storage is a multiple of the word width of the main storage, since typically parts of program code mostly cover multiple consecutive main storage words in the main storage.
Correspondingly, a memory address based cache controlling mechanism may be advantageous if larger numbers of consecutive data may be addressed to be treated in the same way, that is to either be cached or not to be cached. However, a memory address based cache controlling mechanism may be disadvantageous if smaller numbers of consecutive data should be treated differently in terms of caching, that is a first small number of consecutive data should be cached while a consecutive second number of consecutive data should not be cached. This may for example be the case when a large number of smaller routines of program code should be treated differently.